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| rev. 1.3 1/16 copyright ? 2016 by silicon laboratories SI53019-A01A SI53019-A01A 19-o utput pci e g en 3 b uffer features applications description the SI53019-A01A is a 19-output, current mode hcsl differential clock buffer that meets all of the performance requirements of the intel db1900z specification. th e device is optimized for distributing reference clocks for intel ? quickpath interconnect (intel qpi), pcie gen 1/gen 2/ gen 3/gen 4, sas, sata, and intel sc alable memory interconnect (intel smi) applications. the vco of the device is optimized to support 100 mhz and 133 mhz operation. each differential output can be enabled through i 2 c for maximum flexibility and po wer savings. measuring pcie clock jitter is quick and easy with the silicon labs pcie clock jitter tool. download it for free at www.silabs.com/pcie-learningcenter . ? nineteen 0.7 v current-mode, hcsl pcie gen 3 outputs ? 100 mhz /133 mhz pll operation, supports pcie and qpi ? pll bandwidth sw smbus programming overrides the latch value from hw pin ? 9 selectable smbus addresses ? fixed external feedback path ? 8 dedicated oe pin ? pll or bypass mode ? spread spectrum tolerable ? 50 ps output-to-output skew ? fixed 0 ps input to output delay ? low phase jitter (intel qpi, pcie gen 1/gen 2/gen 3/gen 4 common clock compliant ? gen 3 srns compliant ? 100 ps input-to-output delay ? extended temperature: ?40 to 85 c ? package: 72-pin qfn ? server ? storage ? data center ? network security patents pending ordering information: see page 32. pin assignments SI53019-A01A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 vdda gnda hbw_bypass_lbw pwrgd / pwrdn gnd vddr clk_in clk_in sa_0 sda scl sa_1 fb_out gnd dif_7 dif_7 dif_6 dif_6 oe6 vdd dif_5 dif_5 dif_4 dif_4 oe5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dif_11 dif_11 dif_10 dif_10 gnd vdd dif_9 dif_9 dif_8 dif_8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 dif_0 dif_0 gnd dif_1 dif_1 vdd dif_2 dif_2 dif_3 dif_3 vdd oe7 oe10 vdd oe12 dif_12 dif_12 dif_13 dif_13 dif_14 dif_14 65 66 67 68 69 70 71 72 dif_15 dif_15 dif_16 dif_16 dif_17 dif_17 dif_18 dif_18 fb_out iref fb_in fb_in 100m_133m oe8 oe11 oe9
SI53019-A01A 2 rev. 1.3 functional block diagram fb_out dif_[18:0] ssc compatible pll control logic scl sda pwrgd / pwrdn sa_1 sa_0 hbw_bypass_lbw 100m_133 clk_in clk_in fb_in fb_in oe(5_12) iref 8 SI53019-A01A rev. 1.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1. clk_in, clk_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. 100m_133m?frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3. sa_0, sa_1?address select ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4. ckpwrgd/pwrdn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.5. hbw_bypass_lbw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6. miscellaneous requirem ents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. input edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2. termination of differenti al outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.1. byte read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.2. block read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. pin descriptions: 72-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. power filtering example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1. ferrite bead power filter ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9.1. 10x10 mm 72-qfn package land patt ern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SI53019-A01A 4 rev. 1.3 1. electrical specifications table 1. dc operating characteristics 1 v dd_a = 3.3 v5%, v dd =3.3v5% parameter symbol test condition min max unit 3.3 v core supply voltage vdd/vdd_a 3.3 v 5% 3.135 3.465 v 3.3 v input high voltage v ih v dd 2.0 v dd +0.3 v 3.3 v input low voltage v il vss?0.3 0.8 v input leakage current 2 i il 0 < vin < v dd ?5 +5 a 3.3 v input high voltage 3 v ih_fs v dd 0.7 v dd +0.3 v 3.3 v input low voltage 3 v il_fs vss?0.3 0.35 v 3.3 v input low voltage v il_tri 0 0.9 v 3.3 v input med voltage v im_tri 1.3 1.8 v 3.3 v input high voltage v ih_tri 2.4 v dd v 3.3 v output high voltage 4 v oh i oh =?1ma 2.4 ? v 3.3 v output low voltage 4 v ol i ol =1ma ? 0.4 v input capacitance 5 c in 2.5 4.5 pf output capacitance 5 c out 2.5 4.5 pf pin inductance l pin ?7nh ambient temperature t a no airflow ?40 85 c notes: 1. vdd_io applies to the low-power nmos push-pull hcsl compatible outputs. 2. input leakage current does not include inputs with pull-up or pull-down resistors. inputs with resistors should state current requirements. 3. internal voltage reference is to be used to guarantee v ih _fs and v il _fs thresholds levels over full operating range. 4. signal edge is required to be monotonic when transitioning through this region. 5. ccomp capacitance based on pad metallization and silicon device capacitance. not including pin capacitance. SI53019-A01A rev. 1.3 5 table 2. dif 0.7 v ac timing characteristics (non-spread spectrum mode) 1 parameter symbol clk 100 mhz, 133 mhz unit min typ max clock stabilization time 2 t stab ? 1.5 1.8 ms long term accuracy 3,4,5 l acc ? ? 100 ppm absolute host cl k period (100 mhz) 3,4,6 t abs 9.94900 ? 10.05100 ns absolute host cl k period (133 mhz) 3,4,6 t abs 7.44925 7.55075 ns slew rate 3,4,7 edge_rate 1.0 3.0 4.0 v/ns slew rate matching 3,8,10,11 t rise_mat / t fall_mat ?720% rise time variation 3,8,9 ? trise ? ? 125 ps fall time variation 3,8,9 ? tfall ? ? 125 ps voltage high (typ 0.7 v) 3,8,12 v high 660 750 850 mv voltage low (typ 0.7 v) 3,8,13 v low ?150 15 150 mv notes: 1. unless otherwise noted, all spec ifications in this table apply to all processor frequencies. 2. this is the time from the valid clk_in input clocks and the assertion of the pwrgd signal level at 1.8?2.0 v to the time that stable clocks are output from the buffer chip (pll locked). 3. test configuration is rs = 33.2 ? , rp = 49.9, 2 pf for 100 ? transmission line; rs = 27 ? , rp = 42.2, 2 pf for 85 ? transmission line. 4. measurement taken from differential waveform. 5. using frequency counter with the m easurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 hz, 133,000,000 hz. 6. the average period over any 1 s period of time must be greater than the minimum and less than the maximum specified period. 7. measure taken from differential waveform on a component test board. the edge (slew) rate is measured from ?150 mv to +150 mv on the differential waveform. scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge only valid for rising clock and falling clock . signal must be monotonic through the vol to voh region for trise and tfall. 8. measurement taken from single-ended waveform. 9. measured with oscilloscope, averaging off, using min max statistics. variation is the delta between min and max. 10. measured with oscilloscope, averaging on, the difference between the rising edge rate (average) of clock verses the falling edge rate (average) of clock . 11. rise/fall matching is derived using the following, 2*(trise - tfall) / (trise + tfall). 12. vhigh is defined as the statistical average high value as obtained by using the oscilloscope vhigh math function. 13. vlow is defined as the statistical average low value as obtained by using the oscilloscope vlow math function. 14. measured at crossing point where the instantaneous voltage value of the rising edge of clk equals the falling edge of clk . 15. this measurement refers to the total vari ation from the lowest crossing point to th e highest, regardless of which edge is crossing. 16. the crossing point must meet the absolute and relati ve crossing point specifications simultaneously. 17. vcross(rel) min and max are derived using the following, vc ross(rel) min = 0.250 + 0.5 (vhavg ? 0.700), vcross(rel) max = 0.550 ? 0.5 (0.700 ? vhavg), (see figure 4?5 for further clarification). 18. ? vcross is defined as the total variation of all crossing voltages of rising clock and falling clock . this is the maximum allowed variance in vcro ss for any particular system. 19. overshoot is defined as the absolute value of the maximum voltage. 20. undershoot is defined as the absolute value of the minimum voltage. SI53019-A01A 6 rev. 1.3 maximum voltage 8 v max ? 850 1150 mv minimum voltage 3,8,14,15,16 v min ?300 ? ? mv absolute crossing point voltages vox abs 250 450 550 mv total variation of vcross over all edges 3,8,18 to ta l ? vox ? 14 140 mv vswing 4 vswing 300 ? ? mv duty cycle 3,4 dc 45 ? 55 % maximum voltage (overshoot) 3,8,19 v ovs ??v high + 0.3 v maximum voltage (undershoot) 3,8,20 v uds ??v low ? 0.3 v ringback voltage 3,8 v rb 0.2 ? n/a v table 2. dif 0.7 v ac timing characteristics (non-spread spectrum mode) 1 (continued) parameter symbol clk 100 mhz, 133 mhz unit min typ max notes: 1. unless otherwise noted, all spec ifications in this table apply to all processor frequencies. 2. this is the time from the valid clk_in input clocks and the assertion of the pwrgd signal level at 1.8?2.0 v to the time that stable clocks are output from the buffer chip (pll locked). 3. test configuration is rs = 33.2 ? , rp = 49.9, 2 pf for 100 ? transmission line; rs = 27 ? , rp = 42.2, 2 pf for 85 ? transmission line. 4. measurement taken from differential waveform. 5. using frequency counter with the m easurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 hz, 133,000,000 hz. 6. the average period over any 1 s period of time must be greater than the minimum and less than the maximum specified period. 7. measure taken from differential waveform on a component test board. the edge (slew) rate is measured from ?150 mv to +150 mv on the differential waveform. scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge only valid for rising clock and falling clock . signal must be monotonic through the vol to voh region for trise and tfall. 8. measurement taken from single-ended waveform. 9. measured with oscilloscope, averaging off, using min max statistics. variation is the delta between min and max. 10. measured with oscilloscope, averaging on, the difference between the rising edge rate (average) of clock verses the falling edge rate (average) of clock . 11. rise/fall matching is derived using the following, 2*(trise - tfall) / (trise + tfall). 12. vhigh is defined as the statistical average high value as obtained by using the oscilloscope vhigh math function. 13. vlow is defined as the statistical average low value as obtained by using the oscilloscope vlow math function. 14. measured at crossing point where the instantaneous voltage value of the rising edge of clk equals the falling edge of clk . 15. this measurement refers to the total vari ation from the lowest crossing point to th e highest, regardless of which edge is crossing. 16. the crossing point must meet the absolute and relati ve crossing point specifications simultaneously. 17. vcross(rel) min and max are derived using the following, vc ross(rel) min = 0.250 + 0.5 (vhavg ? 0.700), vcross(rel) max = 0.550 ? 0.5 (0.700 ? vhavg), (see figure 4?5 for further clarification). 18. ? vcross is defined as the total variation of all crossing voltages of rising clock and falling clock . this is the maximum allowed variance in vcro ss for any particular system. 19. overshoot is defined as the absolute value of the maximum voltage. 20. undershoot is defined as the absolute value of the minimum voltage. SI53019-A01A rev. 1.3 7 table 3. smbus characteristics parameter symbol test condition min max unit smbus input low voltage 1 v ilsmb ?0.8v smbus input high voltage 1 v ihsmb 2.1 v ddsmb v smbus output low voltage 1 v olsmb @ i pullup ?0.4v nominal bus voltage 1 v ddsmb @ v ol 2.7 5.5 v smbus sink current 1 i pullup 3v to 5v +/?10% 4 ? ma sclk/sdat rise time 1 t rsmb (max v il ? 0.15) to (min v ih + 0.15) ? 1000 ns sclk/sdat fall time 1 t fsmb (min v ih + 0.15) to (max v il ? 0.15) ? 300 ns smbus operating frequency 1,2 f minsmb minimum operating frequency ? 100 khz notes: 1. guaranteed by design and characterization. 2. the differential input clock must be running for the smbus to be active. table 4. current consumption t a = 0?70 c; supply voltage v dd =3.3v 5% parameter symbol test c ondition min typ max unit operating current idd vdd 100 mhz, cl = full load, rs=33 ? ?310350ma power down current idd vddpd all differential pairs tri-stated ? 6 15 ma SI53019-A01A 8 rev. 1.3 table 5. clock input parameters t a = 0?70 c; supply voltage v dd =3.3v 5% parameter symbol test condition min typ max unit input high voltage v ihdif differential inputs (singled-ended measurement) 600 800 1150 mv input low voltage v ihdif differential inputs (singled-ended measurement) vss-300 0 300 mv input common mode voltage v com common mode input voltage 300 ? 1000 mv input amplitude v swing peak to peak value 300 ? 1450 mv input slew rate dv/dt measured differentially 0.4 ? 8 v/ns input duty cycle measurement from differential wave form 45 50 55 % input jitter?cycle to cycle j dfin differential measurement ? ? 125 ps input frequency f ibyp v dd = 3.3 v, bypass mode 33 ? 150 mhz f ipll v dd = 3.3 v, 100 mhz pll mode 90 100 110 mhz fipll v dd = 3.3 v, 133.33 mhz pll mode 120 133.33 147 mhz input ss modulation rate f modin triangle wave modulation 30 31.5 33 khz SI53019-A01A rev. 1.3 9 table 6. output skew, pll bandwidth and peaking t a = 0?70 c; supply voltage v dd =3.3v 5% parameter test condition min typ max unit clk_in, dif[x:0] input-to-o utput delay in pll mode nominal value 1,2,3,4 ?100 20 100 ps clk_in, dif[x:0] input-to-o utput delay in bypass mode nominal value 2,4,5 2.5 3.4 4.5 ns clk_in, dif[x:0] inpu t-to-output delay variation in pll mode over voltage and temperature 2,4,5 ?50 0 50 ps clk_in, dif[x:0] inpu t-to-output delay variation in bypass mode over voltage and temperature 2,4,5 ?250 ? 250 ps clk_in, dif[x:0] random differential spread spectrum tracking error between 2 db1900z devices in hi bw mode ?1575ps clk_in, dif[x:0] random differential tracking error between 2 db1900z devices in hi bw mode ?35ps (rms) dif[18:0] output-to-output skew across all outputs (common to bypass and pll mode) 1,2,3,4,5 02050ps pll jitter peaking (hbw_bypass_lbw =0) 6 ?0.42.0db pll jitter peaking (hbw_bypass_lbw =1) 6 ?0.12.5db pll bandwidth (hbw_bypass_lbw =0) 7 ?0.71.4mhz pll bandwidth (hbw_bypass_lbw =1) 7 ?24mhz notes: 1. measured into fixed 2 pf load cap. input-to-output skew is measured at the fi rst output edge following the corresponding input. 2. measured from differential cross-po int to differential cross-point. 3. this parameter is determin istic for a given device. 4. measured with scope averaging on to find mean value. 5. all bypass mode input-to-output spe cs refer to the timing between an input edge and the specific output edge created by it. 6. measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter peaking. 7. measured at 3 db down or half power point. SI53019-A01A 10 rev. 1.3 table 7. phase jitter parameter test condition min typ max unit phase jitter pll mode pcie gen 1, common clock 1,2,3 ?3086ps pcie gen 2 low band, common clock f < 1.5 mhz 1,3,4,5 ?1.03.0ps (rms) pcie gen2 high band, common clock 1.5 mhz < f < nyquist 1,3,4,5 ?2.63.1ps (rms) pcie gen 3, common clock (pll bw 2?4 mhz, cdr = 10 mhz) 1,3,4,5 ?0.61.0ps (rms) pcie gen 3 separate reference no spread, srns (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,3,4,5 ? 0.42 0.71 ps (rms) pcie gen 4, common clock (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,4,5,8 ?0.61.0ps (rms) intel ? qpi & intel smi (4.8 gbps or 6.4 gb/s, 100 or 133 mhz, 12 ui) 1,6,7 ?0.250.5 ps (rms) intel qpi & intel smi (8 gb/s, 100 mhz, 12 ui) 1,6 ?0.170.3 ps (rms) intel qpi & intel smi (9.6 gb/s, 100 mhz, 12 ui) 1,6 ?0.150.2 ps (rms) notes: 1. post processed evaluation through intel supplied matlab* scri pts. defined for a ber of 1e-12. measured values at a smaller sample size have to be extrapolated to this ber target. 2. = 0.54 implies a jitter peaking of 3 db. 3. pcie* gen3 filter characteristics are subject to final ra tification by pcisig. check the pci-sig for the latest specification. 4. measured on 100 mhz pcie output using the template file in the intel-supplied clock jitter tool v1.6.3. 5. measured on 100 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 6. measured on 100 mhz, 133 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 7. these jitter numbers are defined for a ber of 1e-12. me asured numbers at a smaller sample size have to be extrapolated to this ber target. 8. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 9. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter . SI53019-A01A rev. 1.3 11 additive phase jitter bypass mode pcie gen 1 1,2,3 ?4?ps pcie gen 2 low band f < 1.5 mhz 1,3,4,5 ?0.08? ps (rms) pcie gen 2 high band 1.5 mhz < f < nyquist 1,3,4,5 ?1?ps (rms) pcie gen 3 (pll bw 2?4 mhz, cdr = 10 mhz) 1,3,4,5 ?0.27? ps (rms) pcie gen 4, common clock (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,4,5,8 ?0.27? ps (rms) intel qpi & intel? smi (4.8 gbps or 6.4 gb/s, 100 or 133 mhz, 12 ui) 1,6,7 ?0.25? ps (rms) intel qpi & intel? smi (8 gb/s, 100 mhz, 12 ui) 1,6 ?0.08? ps (rms) intel qpi & intel? smi (9.6 gb/s, 100 mhz, 12 ui) 1,6 ?0.07? ps (rms) table 7. phase jitter (continued) notes: 1. post processed evaluation through intel supplied matlab* scri pts. defined for a ber of 1e-12. measured values at a smaller sample size have to be extrapolated to this ber target. 2. = 0.54 implies a jitter peaking of 3 db. 3. pcie* gen3 filter characteristics are subject to final ra tification by pcisig. check the pci-sig for the latest specification. 4. measured on 100 mhz pcie output using the template file in the intel-supplied clock jitter tool v1.6.3. 5. measured on 100 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 6. measured on 100 mhz, 133 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 7. these jitter numbers are defined for a ber of 1e-12. me asured numbers at a smaller sample size have to be extrapolated to this ber target. 8. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 9. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter . SI53019-A01A 12 rev. 1.3 table 8. clock periods differential clock outputs with ssc disabled ssc off center freq, mhz measurement window unit 1 clock 1s 0.1s 0.1s 0.1s 1s 1 clock -c-c jitter absper min -ssc short term avg min -ppm long term avg min 0ppm period nominal +ppm long term avg max +ssc short term avg max +c-c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns table 9. clock periods differential clock outputs with ssc enabled ssc on center freq, mhz measurement window unit 1 clock 1s 0.1s 0.1s 0.1s 1s 1 clock -c-c jitter absper min -ssc short term avg min -ppm long term avg min 0ppm period nominal +ppm long term avg max +ssc short term avg max +c-c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns table 10. absolute maximum ratings parameter symbol min max unit 3.3 v core supply voltage 1 vdd/vdd_a ? 4.6 v 3.3 v input high voltage 1,2 vih ? v dd +0.5 v v 3.3 v input low voltage 1 vil ?0.5 ? v storage temperature 1 t s ?65 150 c input esd protection 3 esd 2000 ? v notes: 1. consult manufacturer regarding extended operation in excess of normal dc operating parameters. 2. maximum vih is not to exceed maximum v dd . 3. human body model. SI53019-A01A rev. 1.3 13 2. functional description figure 1. SI53019-A01A functional block diagram table 11. functionality at power up (pll mode) 100m_133m clk_in (mhz) conditions 1100 clk_in 0 133.33 clk_in table 12. pll operating mode readback table hbw_bypass_lbw byte 0, bit 7 byte 0, bit 6 mode low 0 0 pll low bw mid (bypass) 0 1 bypass high 1 1 pll high bw fb_out dif_[18:0] ssc compatible pll control logic scl sda pwrgd / pwrdn sa_1 sa_0 hbw_bypass_lbw 100m_133 clk_in clk_in fb_in fb_in oe(5_12) iref 8 SI53019-A01A 14 rev. 1.3 table 13. tri-level input thresholds parameter voltage low <0.8 v mid 1.2 SI53019-A01A rev. 1.3 15 2.1. clk_in, clk_in the differential input clock is expected to be sourced from a clock synthesizer or pch. 2.2. 100m_133m ?frequency selection the SI53019-A01A is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 mhz. 100m_133m is a hardware input pin, which programs the appro priate output frequency of the differential outputs. note that the clk_in frequency must be equal to the clk_out frequency, meaning SI53019-A01A is operated in 1:1 mode only. frequency selection can be enabled by the 100m_133m hardware pin. an external pull-up or pull- down resistor is attached to this pin to select the input/output frequ ency. the functionality is summarized in table 16. note: all differential outputs transition from 100 to 133 mhz or from 133 to 100 mhz in a glitch free manner. 2.3. sa_0, sa_1? address selection sa_0 and sa_1 are tri-level hardware pins, which program the appropriate address for the SI53019-A01A. the two tri-level input pins can configure the device to nine different addresses. table 16. frequency program table 100m_133m optimized frequency (dif_in = dif_x) 0133.33mhz 1100.00mhz table 17. smbus address table sa_1 sa_0 smbus address ll d8 lm da lh de ml c2 mm c4 mh c6 hl ca hm cc hh ce SI53019-A01A 16 rev. 1.3 2.4. ckpwrgd/pwrdn ckpwrgd is asserted high and deassert ed low. deassertion of pwrgd (pullin g the signal low) is equivalent to indicating a power-down condition. ckpwrgd (assertion) is used by the SI53019-A01A to sample initial configurations, such as frequency select condition an d sa selections. after ckpwrgd has been asserted high for the first time, the pin becomes a pwrdn (power down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power-saving mode. pwrdn is a completely asynchronous active low input. when entering power-saving mode, pwrdn should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. when pwrdn is asserted low, all clocks will be disabled prior to turning off the vco. when pwrdn is deasserted high, all clocks will start and stop witho ut any abnormal behavior and will meet all ac and dc parameters. note: the assertion and deassertion of pwrdn is absolutely asynchronous. warning: disabling of the clk_in input clock prior to assertion of pwrdn is an undefined mode and not recommended. operation in this mode may result in gl itches, excessive frequency shifting, etc. table 18. ckpwrgd/pwrdn functionality ckpwrgd/ pwrdn dif_in/ dinf_in# smbus en bit oe# pin dif(5:12) dif(5:12)# other dif/ dif# fbout_nc/ fbout_nc# pll state 0 x x x hi-z* hi-z* hi-z* off 1 running 0 x hi-z* hi-z* running on 1 0 running running running on 1 1 hi-z* running running on *note: due to external pull down resistors, hi-z results in low/low on the true/complement outputs. SI53019-A01A rev. 1.3 17 2.4.1. pwrdn assertion when pwrdn is sampled low by two consecutive rising edges of dif , all differential outputs must be held tri- state/tri-state on the next dif high-to-low transition. the device will put all outputs in high impedance mode, and all outputs will be pulled low by th e external terminating resistors. figure 2. pwrdn assertion 2.4.2. ckpwrgd assertion the power-up latency is to be less than 1.8 ms. this is t he time from a valid clk_in input clock and the assertion of the pwrgd signal to the time that stable clocks are outp ut from the device (pll locked). all differential outputs stopped in a tri-state/tri-state condition resulting from power down must be driven high in less than 300 s of pwrdn deassertion to a voltage greater than 200 mv. figure 3. pwrdg assertion (pwrdown?deassertion) pwrdwn dif dif tstable <1.8 ms tdrive_pwrdn# <300 s; > 200 mv dif dif pwrgd SI53019-A01A 18 rev. 1.3 2.5. hbw_bypass_lbw the hbw_bypass_lbw pin is a tri-level function input pin (refer to table 1 for vil_tri, vim_tri, and vih_tri signal levels). it is used to select between pll high-bandwidth, pll bypass mode, or pll low-bandwidth mode. in pll bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. in the case of pll mode, the input clock is passed through a pll to reduce high-frequency jitter. the pll hbw, bypass, and pll lbw modes may be selected by assert ing the hbw_bypass_lbw input pin to the appropriate level described in table 19. the SI53019-A01A has the ability to override the latch value of the pll operating mode from hardware strap pin 5 via the use of byte 0 and bits 2 and 1. byte 0 bit 3 must be set to 1 to allow the user to change bits 2 and 1, affecting the pll. bits 7 and 6 will a lways read back the or iginal latched value. a wa rm reset of the system will have to be accomplished if the user changes these bits. 2.6. miscellaneous requirements data transfer rate: 100 kbps (standard mode) is the base func tionality required. fast mode (400 kbps) functionality is optional. logic levels: smbus logic levels are based on a percentage of v dd for the controller and other devices on the bus. assume all devices are based on a 3.3 v supply. clock stretching: the clock buffer must not hold/stretch the scl or sda lines low for more than 10 ms. clock stretching is discouraged and should on ly be used as a last resort. stretc hing the clock/data lines for longer than this time puts the device in an error/time-out mode and may not be supported in all platforms. it is assumed that all data transfers can be completed as specifie d without the use of cl ock/data stretching. general call: it is assumed that the clock buffer will no t have to respond to the ?general call.? electrical characteristics: all electrical characteristics must meet the standard mode specifications found in section 3 of the smbus 2.0 specification. pull-up resistors: any internal resistor pull-ups on the sdata an d sclk inputs must be stated in the individual data sheet. the use of internal pull-ups on these pins of below 100 k is discouraged. assume that the board designer will use a single external pu ll-up resistor for each line and th at these values are in the 5?6 k ? range. assume one smbus device per dimm (serial presence detect), one smbus controller, one clock buffer, one clock driver plus one/two more smbus devices on th e platform for capacitive loading purposes. input glitch filters: only fast mode smbus devices require input g litch filters to suppress bus noise. the clock buffer is specified as a standard mode device and is not re quired to support this featur e. however, it is considered a good design practice to include the filters. pwrdn : if a clock buffer is placed in pwrdn mode, the sdata and sclk inputs must be tri-stated and the device must retain all programming information. i dd current due to the smbus circuitry must be characterized and in the data sheet. table 19. pll bandwidth and readback table hbw_bypass_lbw pin mode byte 0, bit 7 byte 0, bit 6 llbw00 m bypass 0 1 hhbw11 SI53019-A01A rev. 1.3 19 3. test and measurement setup 3.1. input edge input edge rate is based on single-ended measurement. this is the minimum input edge rate at which the si53019- a01a is guaranteed to meet a ll performance specifications. 3.1.1. measurement points for differential figure 4. measurement points for rise time and fall time figure 5. single-ended measurement points for v ovs , v uds , v rb table 20. input edge rate frequency min max unit 100 mhz 0.35 n/a v/ns 133 mhz 0.35 n/a v/ns +150 mv -150 mv slew_rise +150 mv -150 mv slew_fall 0.0 v v_swing 0.0 v diff vovs vhigh vrb vlow vrb vuds SI53019-A01A 20 rev. 1.3 figure 6. differential (clock?clock ) measurement points (t period , duty cycle, jitter) 3.2. termination of differential outputs all differential outputs are to be tested into a 100 ? or 85 ? differential impedance transmission line. source terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be supported. for cpu outputs, a maximum trace length of 10? and a maximum of 200 mhz are assumed. for src clocks, a maximum trace length of 16? and maximum freq uency of 100 mhz is assumed. for frequencies beyond 200 mhz, trace lengths must be restrict ed to avoid signal integrity problems. 3.2.1. termination of differential current mode hcsl outputs figure 7. 0.7 v configuration test load board termination table 21. differential output termination clock iref ( ? ) board trace impedance rs rp unit diff clocks?50 ? configuration 475 100 33+ 5% 50 ? diff clocks?43 ? configuration 412 85 27+ 5% 42.2 or 43.2 ? tperiod low duty cycle % high duty cycle % skew measurement point 0.000 v differential ? zo r s r s 10 ? inches r p r p 2pf 2pf SI53019-A01A rev. 1.3 21 4. control registers 4.1. byte read/write reading or writing a register in an smbus slave device in byte mode always involv es specifying the register number. 4.1.1. byte read the standard byte read is as shown in figure 8. it is an extension of the byte write. the write start condition is repeated; then the slave device starts sending data, and the master acknowledges it until the last byte is sent. the master terminates the transfer with a nak, then a stop condition. for byte operation, the 2 x 7th bit of the command byte must be set. for block operations, the 2 x 7th bit must be reset. if the bit is not set, the next byte must be the byte transfer count. figure 8. byte read protocol 4.1.2. byte write figure 9 illustrates a simple, typical byte write. for byte operati on, the 2 x 7th bit of the command byte must be set. for block operations, the 2 x 7th bit must be reset. if the bit is not set, the next byte must be the by te transfer count. the count can be between 1 and 32. it is not allowed to be zero or to exceed 32. figure 9. byte write protocol slave t wr a command slave a rd data byte 0 n p a r command start condition byte read protocol acknowledge repeat start not ack stop condition register # to read 2 x 7 bit = 1 1711 8 117 1 1811 master to slave to slave t wr a command data byte 0 a command start condition byte write protocol acknowledge register # to write 2 x 7 bit = 1 1711 8 1 8 1 1 master to slave to a p stop condition SI53019-A01A 22 rev. 1.3 4.2. block read/write 4.2.1. block read after the slave address is sent with the r/w condition bit set, the command byte is sent with the msb = 0. the slave acknowledges the register index in the command by te. the master sends a repeat start function. after the slave acknowledges this, the slave s ends the number of bytes it wants to transfer (>0 and <33). the master acknowledges each byte except the last and sends a stop function. figure 10. block read protocol 4.2.2. block write after the slave address is sent with the r/w condition bi t not set, the command byte is sent with the msb = 0. the lower seven bits indicate the register at which to start the transfer. if the command byte is 00h, the slave device will be compatible with existing block mode slave devices. the next byte of a write must be the count of bytes that the master will transfer to the slave device. the byte count must be greater than zero and less than 33. following this byte are the data bytes to be transferred to the slave device. the slave device alwa ys acknowledges each byte received. the transfer is terminated after the slav e sends the ack and the mast er sends a stop function. figure 11. block write protocol slave t wr a command code command start condition block read protocol acknowledge repeat start register # to read 2 x 7 bit = 1 1711 8 master to slave to slave a rd a r 11 7 1 1 data byte a data byte 0 a data byte 1 n p 8181811 not acknowledge stop condition slave address t wr a command command bit start condition block write protocol acknowledge register # to write 2 x 7 bit = 0 1711 8 master to slave to a 1 data byte 0 a data byte 1 a p 181811 stop condition byte count = 2 a 8 SI53019-A01A rev. 1.3 23 4.3. control registers table 22. byte 0: pll mode and frequency select register bit pin # name control function 0 1 type default 0 4 100m_133m# frequency select readback 133 mhz 100 mhz r latch 1 reserved 0 2 reserved 0 3 67/66 output enable dif 16 output control, overrides oe# pin 1 4 70/69 output enable dif 17 output control, overrides oe# pin 1 5 72/71 output enable dif 18 output control, overrides oe# pin 1 6 5 pll mode 0 pll operating mode readback 0 see pll operating mode readback table rlatch 7 5 pll mode1 pll operating mode readback 1 rlatch table 23. byte 1: output enable control register bit pin # description if bit = 0 if bit = 1 type default 0 19/20 output enable dif 0 output control, overrides oe# pin hi-z enabled rw 1 1 22/23 output enable dif 1 output control, overrides oe# pin rw 1 2 24/25 output enable dif 2 output control, overrides oe# pin rw 1 3 27/28 output enable dif 3 output control, overrides oe# pin rw 1 4 29/30 output enable dif 4 output control, overrides oe# pin rw 1 5 32/33 output enable dif 5 output control, overrides oe# pin rw 1 6 35/36 output enable dif 6 output control, overrides oe# pin rw 1 7 39/38 output enable dif 7 output control, overrides oe# pin rw 1 SI53019-A01A 24 rev. 1.3 table 24. byte 2: output enable control register bit pin # description control function if bit = 0 if bit = 1 type default 0 42/41 output enable dif 8 output control, overrides oe# pin hi-z enabled rw 1 1 47/46 output enable dif 9 output control, overrides oe# pin rw 1 2 50/49 output enable dif 10 output control, overrides oe# pin rw 1 3 53/52 output enable dif 11 output control, overrides oe# pin rw 1 4 56/55 output enable dif 12 output control, overrides oe# pin rw 1 5 60/59 output enable dif 13 output control, overrides oe# pin rw 1 6 62/61 output enable dif 14 output control, overrides oe# pin rw 1 7 65/64 output enable dif 15 output control, overrides oe# pin rw 1 table 25. byte 3: output enable pin status readback register bit pin # description control function if bit = 0 if bit = 1 type default 0 34 oe_rb5 real time readback of oe5 oe# pin low oe# pin high rreal time 1 37 oe_rb6 real time readback of oe6 rreal time 2 40 oe_rb7 real time readback of oe7 rreal time 3 43 oe_rb8 real time readback of oe8 rreal time 4 48 oe_rb9 real time readback of oe9 rreal time 5 51 oe_rb10 real time readback of oe10 rreal time 6 54 oe_rb11 real time readback of oe11 rreal time 7 57 oe_rb12 real time readback of oe12 rreal time SI53019-A01A rev. 1.3 25 table 26. byte 4: reserved control register bit pin # description control function if bit = 0 if bit = 1 type default 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 table 27. byte 5: vendor/revision identification control register bit pin # description control functio n if bit = 0 if bit = 1 type default 0 ? vendor id bit 0 vendor id r 1 1 ? vendor id bit 1 r 0 2 ? vendor id bit 2 r 0 3 ? vendor id bit 3 r 0 4 ? revision code bit 0 revision id ?a01a = 0001 ?a02a = 0010 r x 5 ? revision code bit 1 r x 6 ? revision code bit 2 r x 7 ? revision code bit 3 r x table 28. byte 6: device id control register bit pin # description control function if bit = 0 if bit = 1 type default 0 ? device id 0 r 1 1 ? device id 1 r 1 2 ? device id 2 r 0 3 ? device id 3 r 1 4 ? device id 4 r 1 5 ? device id 5 r 0 6 ? device id 6 r 1 7 ? device id 7 (msb) r 1 SI53019-A01A 26 rev. 1.3 table 29. byte 7: byte count register bit pin # description control functions if bit = 0 if bit = 1 type default 0 ? bc0 writing to this register configures how many bytes will be read back. default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. rw 0 1 ? bc1 rw 0 2 ? bc2 rw 0 3 ? bc3 rw 1 4 ? bc4 rw 0 5 reserved 0 6 reserved 0 7 reserved 0 SI53019-A01A rev. 1.3 27 5. pin descriptions: 72-pin qfn SI53019-A01A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 vdda gnda hbw_bypass_lbw pwrgd / pwrdn gnd vddr clk_in clk_in sa_0 sda scl sa_1 fb_out gnd dif_7 dif_7 dif_6 dif_6 oe6 vdd dif_5 dif_5 dif_4 dif_4 oe5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dif_11 dif_11 dif_10 dif_10 gnd vdd dif_9 dif_9 dif_8 dif_8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 dif_0 dif_0 gnd dif_1 dif_1 vdd dif_2 dif_2 dif_3 dif_3 vdd oe7 oe10 vdd oe12 dif_12 dif_12 dif_13 dif_13 dif_14 dif_14 65 66 67 68 69 70 71 72 dif_15 dif_15 dif_16 dif_16 dif_17 dif_17 dif_18 dif_18 fb_out iref fb_in fb_in 100m_133m oe8 oe11 oe9 SI53019-A01A 28 rev. 1.3 table 30. SI53019-A01A 72-pin qfn descriptions pin # name type description 1vdda 3.3 v 3.3 v power supply for pll. 2 gnda gnd ground for pll. 3iref out this pin establishes the reference fo r the differential current mode output pairs. it requires a fixed precision resistor to ground. 475 ?? is the standard value for 100 ? differential impedance. other impedances require different values. 4 100m_133m i,se 3.3 v tolerant inputs for input/output frequency selection. an external pull- up or pull-down resistor is attached to this pin to select the input/output frequency. high = 100 mhz output low = 133 mhz output 5 hbw_bypass_lbw i, se tri-level input for selecting the pll bandwidth or bypass mode. high = high bw mode med = bypass mode low = low bw mode 6 pwrgd/pwrdn i 3.3 v lvttl input to power up or power down the device. 7gnd gnd ground for outputs. 8 vddr vdd 3.3 v power supply for differential input receiver. this vddr should be treated as an analog power rail and filtered appropriately. 9 clk_in i, dif 0.7 v differential true input. 10 clk_in i, dif 0.7 v differential input. 11 sa_0 i,pu 3.3 v lvttl input selecting the address. tr i-level input. 12 sda i/o open collector smbus data. 13 scl i/o smbus slave clock input. 14 sa_1 i,pu 3.3 v lvttl input selecting the address. tr i-level input. 15 fb_in i/o true differential feedback input. provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. 16 fb_in i/o complementary differenti al feedback input. provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. 17 fb_out i/o complementary differential feedback output, provides f eedback signal to the pll for synchronization with input clock to eliminate phase error. 18 fb_out i/o true differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. 19 dif_0 o, dif 0.7 v differential true clock output. 20 dif_0 o, dif 0.7 v differential co mplimentary clock output. 21 vdd vdd power supply for differential outputs. 22 dif_1 o, dif 0.7 v differential true clock output. SI53019-A01A rev. 1.3 29 23 dif_1 o, dif 0.7 v differential co mplimentary clock output. 24 dif_2 o, dif 0.7 v differential true clock output. 25 dif_2 o, dif 0.7 v differential co mplimentary clock output. 26 gnd gnd ground for outputs. 27 dif_3 o, dif 0.7 v differential true clock output. 28 dif_3 o, dif 0.7 v differential co mplimentary clock output. 29 dif_4 o, dif 0.7 v differential true clock output. 30 dif_4 o, dif 0.7 v differential co mplimentary clock output. 31 vdd 3.3 v 3.3 v power supply 32 dif_5 o, dif 0.7 v differential true clock output. 33 dif_5 o, dif 0.7 v differential co mplimentary clock output. 34 oe5 in active low input fo r enabling dif pair 5 1 = disable outputs, 0 = enable outputs 35 dif_6 o, dif 0.7 v differential true clock output. 36 dif_6 o, dif 0.7 v differential co mplimentary clock output. 37 oe6 in active low input fo r enabling dif pair 6 1 = disable outputs, 0 = enable outputs 38 dif_7 o, dif 0.7 v differential true clock output. 39 dif_7 o, dif 0.7 v differential co mplimentary clock output. 40 oe7 in active low input fo r enabling dif pair 7 1 = disable outputs, 0 = enable outputs 41 dif_8 o, dif 0.7 v differential true clock output. 42 dif_8 o, dif 0.7 v differential co mplimentary clock output. 43 oe8 in active low input fo r enabling dif pair 8 1 = disable outputs, 0 = enable outputs 44 gnd gnd ground for outputs. 45 vdd 3.3 v 3.3 v power supply 46 dif_9 o, dif 0.7 v differential true clock output. 47 dif_9 o, dif 0.7 v differential co mplimentary clock output. 48 oe9 in active low input fo r enabling dif pair 9 1 = disable outputs, 0 = enable outputs 49 dif_10 o, dif 0.7 v differential true clock output. table 30. SI53019-A01A 72-pin qfn descriptions pin # name type description SI53019-A01A 30 rev. 1.3 50 dif_10 o, dif 0.7 v differential co mplimentary clock output. 51 oe10 in active low input fo r enabling dif pair 10 1 = disable outputs, 0 = enable outputs 52 dif_11 o, dif 0.7 v differential true clock output. 53 dif_11 o, dif 0.7 v differential co mplimentary clock output. 54 oe11 in active low input fo r enabling dif pair 11 1 = disable outputs, 0 = enable outputs 55 dif_12 o, dif 0.7 v differential true clock output. 56 dif_12 o, dif 0.7 v differential co mplimentary clock output. 57 oe12 in active low input fo r enabling dif pair 12 1 = disable outputs, 0 = enable outputs 58 vdd 3.3 v 3.3 v power supply 59 dif_13 o, dif 0.7 v differential true clock output. 60 dif_13 o, dif 0.7 v differential co mplimentary clock output. 61 dif_14 o, dif 0.7 v differential true clock output. 62 dif_14 o, dif 0.7 v differential co mplimentary clock output. 63 gnd gnd ground for outputs. 64 dif_15 o, dif 0.7 v differential true clock output. 65 dif_15 o, dif 0.7 v differential co mplimentary clock output. 66 dif_16 o, dif 0.7 v differential true clock output. 67 dif_16 o, dif 0.7 v differential co mplimentary clock output. 68 vdd 3.3 v 3.3 v power supply 69 dif_17 o, dif 0.7 v differential true clock output. 70 dif_17 o, dif 0.7 v differential co mplimentary clock output. 71 dif_18 o, dif 0.7 v differential true clock output. 72 dif_18 o, dif 0.7 v differential co mplimentary clock output. 73 gnd gnd ground for outputs. table 30. SI53019-A01A 72-pin qfn descriptions pin # name type description SI53019-A01A rev. 1.3 31 6. power filtering example 6.1. ferrite bead power filtering recommended ferrite be ad filtering equival ent to the following: figure 12. schematic example of the SI53019-A01A power filtering SI53019-A01A 32 rev. 1.3 7. ordering guide part number package type temperature lead-free SI53019-A01Agm 72-pin qfn extended, ?40 to 85 ? c SI53019-A01Agmr 72-pin qfn?tape and reel extended, ?40 to 85 ? c SI53019-A01A rev. 1.3 33 8. package outline figure 13 illustrates the pack age details for the SI53019-A01A. table 31 lis ts the values for the dimensions shown in the illustration. figure 13. 72-pin quad flat no lead (qfn) package table 31. package diagram dimensions 1,2,3,4 dimension min nom max dimension min nom max a 0.80 0.85 0.90 e2 5.90 6.00 6.10 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 aaa 0.10 d 10.00 bsc. bbb 0.10 d2 5.90 6.00 6.10 ccc 0.08 e 0.50 bsc. ddd 0.10 e 10.00 bsc. eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specif ication for small body components. SI53019-A01A 34 rev. 1.3 9. pcb land pattern 9.1. 10x10 mm 72-qfn package land pattern ? SI53019-A01A rev. 1.3 35 table 32. pcb land pattern dimension mm c1 9.90 c2 9.90 e0.50 x1 0.30 y1 0.85 x2 6.10 y2 6.10 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum ma terial condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 8. a 3x3 array of 1.45 mm square openings on 2. 00 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI53019-A01A 36 rev. 1.3 d ocument c hange l ist revision 1.0 to revision 1.1 ? updated descriptions for pin15, pin16, pin17, and pin18 in table 30. revision 1.1 to revision 1.2 ? updated features on page 1. ? updated description on page 1. ? updated specs in table 7, ?phase jitter,? on page 10. ? updated the package drawing and table. revision 1.2 to revision 1.3 january 20, 2016 ? updated the package drawing and table. ? updated the land pattern drawing and table. ? correct specs in table 1 on page 4. disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com |
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